A reduced clock-swing flip-flop (RCSFF) for 63% power reduction-Reference-Cited by-同舟云学术

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A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

Published:1998-05 Issue:5 Volume:33 Page:807-811
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kawaguchi H.,Sakurai T.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx4/4/14629/00668997.pdf?arnumber=668997

Cited by 125 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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4. Design and Speed Analysis of Low Power Single and Double Edge Triggered Flip Flop with Pulse Signal Feed-Through Scheme;International Journal of Electrical and Electronics Research;2022-12-30

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