VLFF - A Very Low-power Flip-flop with only Two Clock Transistors
Author:
Affiliation:
1. University of Waterloo,ECE Department,Waterloo,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10256666/10256705/10257122.pdf?arnumber=10257122
Reference20 articles.
1. A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS
2. The cross charge-control flip-flop: a low-power and high-speed flip-flop suitable for mobile application SoCs
3. Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
4. 27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications
5. Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
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