An Overview of Low-Power VLSI Design Methods for CMOS and CNTFET-Based Circuits
Author:
Affiliation:
1. Institute of Aeronautical Engineering,Hyderabad
2. Lords Institute of Engineering and Technology,Department of ECE,Hyderabad
3. CMR College of Engineering & Technology,Department of ECE,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10128170/10128171/10128227.pdf?arnumber=10128227
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2. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
3. Multi-Voltage CMOS Circuit Design
4. Efficient timing element design featuring low power vlsi application;nagarajan;International Journal of Engineering and Technology (IJET),2016
5. A low-swing clock double-edge triggered flip-flop
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