A low-swing clock double-edge triggered flip-flop-Reference-Cited by-同舟云学术

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A low-swing clock double-edge triggered flip-flop

Published:2002-05 Issue:5 Volume:37 Page:648-652
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chulwoo Kim ,Sung-Mo Kang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/21525/00997859.pdf?arnumber=997859

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP;REV ROUM SCI TECH-EL;2023

2. An Overview of Low-Power VLSI Design Methods for CMOS and CNTFET-Based Circuits;2023 International Conference on Computer Communication and Informatics (ICCCI);2023-01-23

3. Design of Low-power Quad-edge-triggered Flip-flop at Switch Level;2022 4th International Conference on Intelligent Control, Measurement and Signal Processing (ICMSP);2022-07-08

4. Anti-interference low-power double-edge triggered flip-flop based on C-elements;Tsinghua Science and Technology;2022-02

5. Design of odd-even multiplexer for all-edges-triggered flip-flops;International Journal of Electronics Letters;2021-03-30

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