A power-efficient, single-phase, contention-free flip-flop with only three clock transistors

Author:

Maheshwari Yugal KishoreORCID,Sachdev Manoj

Publisher

Elsevier BV

Reference42 articles.

1. A 77% energy-saving 22-transistor single-phase-clocking d-flip-flop with adaptive-coupling configuration in 40 nm cmos;Teh,2011

2. A fully static topologically-compressed 21-transistor flip-flop with 75% power saving;Kawai;IEEE J. Solid-State Circuits,2014

3. A novel high-speed sense-amplifier-based flip-flop;Strollo;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2005

4. High-performance quaternary latch and d-type flip-flop with selective outputs;Safipoor;Microelectron. J.,2021

5. A novel design for ultra-low power pulse-triggered d-flip-flop with optimized leakage power;Karimi;Integration,2018

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