A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving-Reference-Cited by-同舟云学术

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A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving

Published:2014-11 Issue:11 Volume:49 Page:2526-2533
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kawai Natsumi,Takayama Shinichi,Masumi Junya,Kikuchi Naoto,Itoh Yasuo,Ogawa Kyosuke,Ugawa Akimitsu,Suzuki Hiroaki,Tanaka Yasunori

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6936396/06851220.pdf?arnumber=6851220

Cited by 67 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A power-efficient, single-phase, contention-free flip-flop with only three clock transistors;Microelectronics Journal;2024-10

2. Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop;IETE Journal of Research;2024-05-21

3. A Low-Power Single-Phase Split-Controlled Flip-Flop With No Redundant Switching;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A Redundant-Transition-Free and Contention-Free Change-Sensing Flip-Flop;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-05

5. Design and implementation of low power D flip flop for embedded application;AIP Conference Proceedings;2024

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