An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance-Reference-Cited by-同舟云学术

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An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Chou Chung-Cheng,Lin Zheng-Jun,Tseng Pei-Ling,Li Chih-Feng,Chang Chih-Yang,Chen Wei-Chi,Chih Yu-Der,Chang Tsung-Yung Jonathan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310392.pdf?arnumber=8310392

Cited by 38 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro;IEEE Journal of Solid-State Circuits;2024-09

2. Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09

3. A Subthreshold Adaptive-Reference Leakage- Compensation Sensing Scheme for 3D PCM With Enhanced Sensing Margin and Endurance;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

4. EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage;IEEE Journal of Solid-State Circuits;2024-07

5. A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection;IEEE Journal of Solid-State Circuits;2024-07

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