Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro-Reference-Cited by-同舟云学术

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Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro

Published:2024-09 Issue:9 Volume:59 Page:3045-3057
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Giraud Bastien¹^ORCID,Ricavy Sebastien²^ORCID,Laffond Cyrille¹,Sever Ilan³,Gherman Valentin¹^ORCID,Lepin Florent¹^ORCID,Diallo Mariam¹,Zenati Khadija¹,Dumas Sylvain²^ORCID,Guille Olivier²,Vershkov Maxim³,Bricalli Alessandro³,Piccolboni Giuseppe³,Noel Jean-Philippe¹^ORCID,Samir Anass²,Pillonnet Gaël²^ORCID,Thonnart Yvain¹^ORCID,Molas Gabriel³^ORCID

Affiliation:

1. Univ. Grenoble Alpes, CEA, List, Grenoble, France

2. Univ. Grenoble Alpes, CEA, Leti, Grenoble, France

3. Weebit Nano Ltd., Hod Hasharon, Israel

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4/10648889/10509675.pdf?arnumber=10509675

Reference25 articles.

1. Reliability of 28nm embedded RRAM for consumer and industrial products

2. Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

3. Cell-to-Cell Fundamental Variability Limits Investigation in OxRRAM Arrays

4. 16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors

5. OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraints

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