Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads-Reference-Cited by-同舟云学术

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Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads

Published:2024-09 Issue:9 Volume:32 Page:1718-1725
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Luo Yuan-Chun¹^ORCID,Lu Anni¹^ORCID,Sharda Janak¹^ORCID,Scherer Moritz²,Tomas Gomez Jorge²^ORCID,Shakib Sarwar Syed²^ORCID,Li Ziyun²^ORCID,Frederick Pinkham Reid²,De Salvo Barbara²^ORCID,Yu Shimeng¹^ORCID

Affiliation:

1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

2. Meta Reality Lab Research, Menlo Park, CA, USA

Funder

CHIMES, one of Semiconductor Research Corporation (SRC)/Defense Advanced Research Projects Agency (DARPA) Joint University Microelectronics Program (JUMP) 2.0 Center.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/92/10648891/10576629.pdf?arnumber=10576629

Reference20 articles.

1. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

2. In-Datacenter Performance Analysis of a Tensor Processing Unit

3. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

4. DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

5. Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

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