FPGA Implementation of High Performance Precise Signed and Unsigned Multiplier using Ternary 6-LUT Architecture-Reference-Cited by-同舟云学术

FPGA Implementation of High Performance Precise Signed and Unsigned Multiplier using Ternary 6-LUT Architecture

Published:2022-07-20 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Inventive Computation Technologies (ICICT)
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Author:

Mahendra Palle¹,Ramesh S R¹

Affiliation:

1. Coimbatore Amrita Vishwa Vidyapeetham,Amrita School of Engineering,Department of Electronics and Communication Engineering,India

Publisher

IEEE

Link

Reference18 articles.

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