Author:
Kumm Martin,Kappauf Johannes,Istoan Matei,Zipf Peter
Cited by
19 articles.
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1. Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
3. AxOMaP
: Designing FPGA-based
A
ppro
x
imate Arithmetic
O
perators using
Ma
thematical
P
rogramming;ACM Transactions on Reconfigurable Technology and Systems;2024-04-30
4. High-throughput and fully-pipelined ciphertext multiplier for homomorphic encryption;IEICE Electronics Express;2024-03-25
5. Fast 32-bit and 48-bit Multipliers for FPGA;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28