Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression-Reference-Cited by-同舟云学术

Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression

Author:

Kakacak Ahmet,Guzel Aydin Emre,Cihangir Ozan,Gören Sezer,Ugurdag H. Fatih

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference17 articles.

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3. Some schemes for parallel multipliers;Dadda;Alta Freq.,1965

4. Efficient high speed compression trees on Xilinx FPGAs;Kumm;Methode. und Beschreib. Zur. Modellier. und Verif. Von. Schalt. und Syst.,2014

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