Author:
Brunie Nicolas,de Dinechin Florent,Istoan Matei,Sergent Guillaume,Illyes Kinga,Popa Bogdan
Cited by
12 articles.
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1. Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
3. High-efficiency Compressor Trees for Latest AMD FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2024-04-30
4. Newton-Raphson Integer Division for Area-Constrained Microcontrollers;2023 IEEE 30th Symposium on Computer Arithmetic (ARITH);2023-09-04
5. Sums of Weighted Bits;Application-Specific Arithmetic;2023-08-23