A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE-Reference-Cited by-同舟云学术

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A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

Published:2021-11-07 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Jin Hyungmin,Byun Jindo,Cho Hyunyoon,Yoon Hojun,Park Jin-Hee,Kim Kyoungsoo,Choi Youngdon,Choi Jung-Hwan,Ko Hyungjong,Lee Sang-Hyun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9634699/9634177/09634750.pdf?arnumber=9634750

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01

2. A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

3. A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

4. A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

5. A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test;2022 IEEE Asian Solid-State Circuits Conference (A-SSCC);2022-11-06

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