A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge
Author:
Affiliation:
1. Seoul National University,Seoul,Korea
2. SK Hynix,Icheon,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10347557/10347908/10347967.pdf?arnumber=10347967
Reference5 articles.
1. A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE
2. A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing
3. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
4. An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS
5. 6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS
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