A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization-Reference-Cited by-同舟云学术

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A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Jin Jahoon¹,Lee Soo-Min¹,Min Kyunghwan¹,Ju Sodam¹,Lim Jihoon¹,Chae Hyunsu¹,Kang Kwonwoo¹,Hong Yunji¹,Jeong Yeongcheol¹,Kim Sang-Ho¹,Lee Jongwoo¹,Kim Joonsuk¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067738.pdf?arnumber=10067738

Reference6 articles.

1. A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS

2. A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

3. 23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller

4. An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching;choi;IEEE JSSC,2018

5. A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

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