A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation
Author:
Affiliation:
1. Seoul National University,Department of Electrical and Computer Engineering,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182132.pdf?arnumber=10182132
Reference12 articles.
1. A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS
2. Feedforward Cherry-Hooper Continuous Time Linear Equalizer in 28-nm CMOS
3. 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
4. 6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS
5. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
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1. A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
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