A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS
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IEEE
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http://xplorestaging.ieee.org/ielx7/9634699/9634177/09634775.pdf?arnumber=9634775
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 14–28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
2. A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS;IEEE Journal of Solid-State Circuits;2023-05
4. A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-09
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