A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS-Reference-Cited by-同舟云学术

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

Published:2023-05 Issue:5 Volume:58 Page:1414-1424
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Jung Woosong¹^ORCID,Lee Kwangho²,Park Kwanseo³^ORCID,Ju Haram²^ORCID,Lee Jinhyung⁴,Jeong Deog-Kyoon¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, South Korea

2. Korea Electronics Technology Institute (KETI), Seongnam, South Korea

3. Department of System Semiconductor Engineering and the School of Electrical and Electronics Engineering, Yonsei University, Seoul, South Korea

4. SK Hynix, Icheon, South Korea

Funder

Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant

Korea Government (MSIT)

Inter-University Semiconductor Research Center (ISRC) of Seoul National University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10107667/09926041.pdf?arnumber=9926041

Reference21 articles.

1. A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects

2. A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery

3. A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

4. Design techniques for a 60 Gb/s 173 mW wireline receiver frontend in 65 nm CMOS technology;han;IEEE J Solid-State Circuits,2016

5. An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS

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1. A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. A 25-Gb/s PAM-4 Baud-rate CDR with High Jitter Tolerance using Shared Sampler Method;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2024-06-30

3. A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

4. A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link;IEEE Access;2023