Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology-Reference-Cited by-同舟云学术

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Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology

Published:2016-04 Issue:4 Volume:51 Page:871-880
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7446371/7437437.pdf?arnumber=7437437

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2024-01

2. A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS;IEEE Journal of Solid-State Circuits;2023-05

3. A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2023-01

4. 6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS;IEICE Electronics Express;2022-11-25

5. A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS;2021 IEEE Asian Solid-State Circuits Conference (A-SSCC);2021-11-07

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