6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Author:

Sun Haoran1,Zhang Yinhang1,Yang Xi1

Affiliation:

1. College of Communication and Electronic Engineering, Jishou University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference32 articles.

1. [1] M. Zhang, et al.: “A 24Gb/s high speed adaptive combined equalizer for backplane communication,” Acta Electronica Sinica 45 (2017) 1608 (DOI: 10.3969/j.issn.0372-2112.2017.07.009).

2. [2] S. Yuan, et al.: “A 70mW 25Gb/s quarter-rate SerDes transmitter and receiver chipset with 40dB of equalization in 65nm CMOS technology,” IEEE Trans. Circuits Syst I, Reg. Papers. 63 (2016) 939 (DOI: 10.1109/TCSI.2016.2555250).

3. [3] P. Manh Ha, et al.: “An adaptive continuous-time linear equalizer using sampled data edge counting,” International Symposium on Communications and Information Technologies (ISCIT) (2019) 192 (DOI: 10.1109/ISCIT.2019.8905130).

4. [4] Y. Chen, et al.: “A 0.002-mm 6.4-mW 10-Gb/s full-rate direct DFE receiver with 59.6% horizontal eye opening under 23.3-dB channel loss at Nyquist frequency,” IEEE Trans. Microw. Theory Techn. 62 (2017) 3107 (DOI: 10.1109/TMTT.2014.2360697).

5. [5] A. Atharav and B. Razavi: “A 56Gb/s 50mW NRZ receiver in 28nm CMOS,” IEEE J. Solid-State Circuits 57 (2022) 54 (DOI: 10.1109/JSSC.2021.3109032).

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