A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test
Author:
Affiliation:
1. EPFL,Neuchâtel,Switzerland
2. Seoul National University,Seoul,Korea
3. SK Hynix,Icheon,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980646.pdf?arnumber=9980646
Reference8 articles.
1. A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator;wu;TVLSI,2016
2. A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE
3. A Low-Power High-Speed Comparator for Precise Applications
4. A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS
5. Generating At-speed array fail maps with low-speed ATE
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement;IEEE Transactions on Instrumentation and Measurement;2023
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