A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test-Reference-Cited by-同舟云学术

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A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test

Published:2022-11-06 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Kye Chan-Ho¹,Kim Jihee²,Baek Kyungmin²,Kim Kahyun²,Pack Sangjin³,Jung Changwon³,Jeong Deog-Kyoon²

Affiliation:

1. EPFL,Neuchâtel,Switzerland

2. Seoul National University,Seoul,Korea

3. SK Hynix,Icheon,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980646.pdf?arnumber=9980646

Reference8 articles.

1. A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator;wu;TVLSI,2016

2. A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

3. A Low-Power High-Speed Comparator for Precise Applications

4. A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS

5. Generating At-speed array fail maps with low-speed ATE

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2024-06-30

2. A Novel Method for LPDDR5 DRAM Jitter Measurement Through De-embedding;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement;IEEE Transactions on Instrumentation and Measurement;2023

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