A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test
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Published:2024-06-30
Issue:3
Volume:24
Page:284-288
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ISSN:2233-4866
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Container-title:JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
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language:en
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Short-container-title:JSTS
Author:
Kye Chan-Ho,Kim Jihee,Jeong Deog-Kyoon,Choo Min-Seong
Publisher
The Institute of Electronics Engineers of Korea