Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement

Author:

Chae Joo-Hyung1ORCID

Affiliation:

1. Department of Electronics and Communications Engineering, Kwangwoon University, Seoul, South Korea

Funder

Excellent Researcher Support Project of Kwangwoon University in 2023

National Research Foundation of Korea (NRF) through Korean Government [Ministry of Science and ICT (MSIT)]

Institute of Information and Communications Technology Planning and Evaluation (IITP) through Korean Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Reference34 articles.

1. A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method;nam;Proc IEEE Int Test Conf,2008

2. An Automated Methodology for the Tracking of Electrical Performance for Memory Test Systems

3. A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS

4. A 10 Gb/s/pin DQS and WCK built-out tester for LPDDR5 DRAM test;kye;Proc IEEE Asian Solid-State Circuits Conf (A-SSCC),2022

5. An ASIC library granular DRAM macro with built-in self test

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