A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS-Reference-Cited by-同舟云学术

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A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS

Published:2015-06 Issue: Volume: Page:
ISSN:
Container-title:2015 Symposium on VLSI Circuits (VLSI Circuits)
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Author:

Elhadidy Osama,Roshan-Zamir Ashkan,Yang Hae-Woong,Palermo Samuel

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7196579/7231231/07231265.pdf?arnumber=7231265

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

2. Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement;IEEE Transactions on Instrumentation and Measurement;2023

3. Spatial multiplexing and optical PAM4 quadruple the date rate in optical fiber systems;Applied Optics;2022-12-07

4. A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation;IEEE Journal of Solid-State Circuits;2022-01

5. Design of a low cost and power efficient 200/400 Gbps optical interconnect using DAC-less simplified PAM4 architecture;Journal of Optical Communications;2021-11-01

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