A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System
Author:
Affiliation:
1. National Central University,Department of Electrical Engineering,Taoyuan,Taiwan
2. National Taipei University,Department of Electrical Engineering,Taipei,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10382705/10382711/10382879.pdf?arnumber=10382879
Reference15 articles.
1. A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS
2. Low-Power CMOS Equalizer Design for 20-Gb/s Systems
3. A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
4. A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS
5. A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor
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