A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8118328/08100715.pdf?arnumber=8100715
Cited by 40 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
2. A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations;2023 20th International SoC Design Conference (ISOCC);2023-10-25
3. A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE);2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
4. A PAM4 transceiver design scheme with threshold adaptive and tap adaptive;EURASIP Journal on Advances in Signal Processing;2023-06-21
5. PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
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