A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET-Reference-Cited by-同舟云学术

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A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

Published:2017-12 Issue:12 Volume:52 Page:3486-3502
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Im Jay^ORCID,Freitas Dave,Roldan Arianne Bantug,Casey Ronan,Chen Stanley,Chou Chuen-Huei Adam,Cronin Tim,Geary Kevin,McLeod Scott,Zhou Lei,Zhuang Ian,Han Jaeduk,Lin Sen,Upadhyaya Parag,Zhang Geoff,Frans Yohan^ORCID,Chang Ken

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8118328/08100715.pdf?arnumber=8100715

Cited by 49 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology;Microelectronics Journal;2024-09

2. A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques;IEEE Journal of Solid-State Circuits;2024-08

3. A 16-Gb/s 3-tap adaptive DFE in 12-nm FinFET CMOS technology;Microelectronics Journal;2024-07

4. A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS;Microelectronics Journal;2024-06

5. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS;Journal of Semiconductors;2024-06-01

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