3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems-Reference-Cited by-同舟云学术

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3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems

Published: Issue: Volume: Page:
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Container-title:Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)
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Author:

Bazargan K.,Kastner R.,Sarrafzadeh M.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/6324/16908/00779029.pdf?arnumber=779029

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hypergraphs and extremal optimization in 3D integrated circuit design automation;Advanced Engineering Informatics;2017-08

2. Using shape grammars and extremal optimization in 3D IC layout design;Microelectronic Engineering;2015-12

3. Floorplacement for Partial Reconfigurable FPGA-Based Systems;International Journal of Reconfigurable Computing;2011

4. Placement and Floorplanning in Dynamically Reconfigurable FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2010-11

5. Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration;ACM Transactions on Design Automation of Electronic Systems;2006-04

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