Placement and Floorplanning in Dynamically Reconfigurable FPGAs

Author:

Montone Alessio1,Santambrogio Marco D.2,Sciuto Donatella1,Memik Seda Ogrenci3

Affiliation:

1. Politecnico di Milano

2. Massachusetts Institute of Technology

3. Northwestern University

Abstract

The aim of this article is to describe a complete partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs and considering communication infrastructure feasibility. This article proposes a novel approach for resource- and reconfiguration- aware floorplanning. Different from existing approaches, our floorplanning algorithm takes specific physical constraints such as resource distribution and the granularity of reconfiguration possible for a given FPGA device into account. Due to the introduction of constraints typical of other problems like partitioning and placement, the proposed approach is named floorplacer in order to underline the great differences with respect to traditional floorplanners. These physical constraints are typically considered at the later placement stage. Different aspects of the problems have been described, focusing particularly on the FPGAs resource heterogeneity and the temporal dimension typical of reconfigurable systems. Once the problem is introduced a comparison among related works has been provided and their limits have been pointed out. Experimental results proved the validity of the proposed approach.

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science

Reference23 articles.

1. Unification of partitioning, placement and floorplanning

2. Fixed-outline floorplanning: enabling hierarchical design

3. Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System

4. Donato A. Ferrandi F. Redaelli M. Santambrogio M. D. and Sciuto D. 2007. Exploiting partial dynamic reconfiguration for SOC design of complex application on FPGA platforms. In VLSI-SOC: From Systems to Silicon. 87--109. Donato A. Ferrandi F. Redaelli M. Santambrogio M. D. and Sciuto D. 2007. Exploiting partial dynamic reconfiguration for SOC design of complex application on FPGA platforms. In VLSI-SOC: From Systems to Silicon . 87--109.

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