Affiliation:
1. University of Pennsylvania, USA
Abstract
Partial Reconfiguration (PR) is a key technique in the application design on modern FPGAs. However, current PR tools heavily rely on the developer to manually conduct PR module definition, floorplanning, and flow control at a low level. The existing PR tools do not consider High-Level-Synthesis languages either, which are of great interest to software developers. We propose HiPR, an open-source framework, to bridge the gap between HLS and PR. HiPR allows the developer to define partially reconfigurable C/C++ functions, instead of Verilog modules, to accelerate the FPGA incremental compilation and automate the flow from C/C++ to bitstreams. We use a lightweight Simulated Annealing floorplanner and show that it can produce high-quality PR floorplans an order of magnitude faster than analytic methods. By mapping Rosetta HLS benchmarks, we demonstrate that the incremental compilation can be accelerated by 3–10 × compared with state-of-the-art Xilinx Vitis flow without performance loss, at the cost of 15-67% one-time overlay set-up time.
Publisher
Association for Computing Machinery (ACM)
Reference61 articles.
1. Amazon. 2022 (Accessed: 2022-12-28). Amazon EC2 F1 Instances. Xilinx. https://aws.amazon.com/ec2/instance-types/f1/ Amazon. 2022 (Accessed: 2022-12-28). Amazon EC2 F1 Instances. Xilinx. https://aws.amazon.com/ec2/instance-types/f1/
2. Floorplanning for partially reconfigurable FPGAs;Banerjee Pritha;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2010
3. Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems
4. Gordon Brebner . 1997. The Swappable Logic Unit: A Paradigm for Virtual Hardware . In FCCM. IEEE , Napa Valley, CA, USA , 77–86. Gordon Brebner. 1997. The Swappable Logic Unit: A Paradigm for Virtual Hardware. In FCCM. IEEE, Napa Valley, CA, USA, 77–86.
5. Finding hard-to-find data plane bugs with a PTA