Hypergraphs and extremal optimization in 3D integrated circuit design automation

Author:

Grzesiak-Kopeć Katarzyna,Oramus Piotr,Ogorzałek Maciej

Publisher

Elsevier BV

Subject

Artificial Intelligence,Information Systems

Reference34 articles.

1. Placement and routing in 3D integrated circuits;Ababei;IEEE Des. Test,2005

2. 3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems;Bazargan;Rapid Syst. Prototyp.,1999

3. Hypergraphs: Combinatorics of Finite Sets;Berge,1989

4. Extremal optimization: heuristics via coevolutionary avalanches;Boettcher;Comput. Sci. Eng.,2000

5. B*-trees: a new representation for non-slicing floorplans;Chang;Des. Automation Conf.,2000

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1. Specification-Driven Evolution of Floor Plan Design;Lecture Notes in Computer Science;2022

2. Evolutionary Methods in House Floor Plan Design;Applied Sciences;2021-09-05

3. A Parallel and Distributed Topological Approach to 3D IC Optimal Layout Design;Artificial Intelligence and Soft Computing;2020

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