A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS-Reference-Cited by-同舟云学术

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A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Published:2015-09 Issue:9 Volume:50 Page:2025-2036
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Szortyka Viki,Shi Qixian,Raczkowski Kuba,Parvais Bertrand,Kuijk Maarten,Wambacq Piet

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7226885/07131584.pdf?arnumber=7131584

Cited by 47 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 21.8–41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller;IEEE Transactions on Microwave Theory and Techniques;2024-09

2. A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A Low Jitter and Low Reference Spur 5GHz PLL with Quadrature Charge-sampling PD in 28nm CMOS Process;IEICE Electronics Express;2024

4. Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

5. Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs;IEEE Journal of Solid-State Circuits;2024-01

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