A 21.8–41.6-GHz Low Jitter and High FoM<i>j</i> Fast-Locking Subsampling PLL With Dead Zone Automatic Controller-Reference-Cited by-同舟云学术

A 21.8–41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

Published:2024-09 Issue:9 Volume:72 Page:5361-5375
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Chen Wen¹^ORCID,Shu Yiyang¹^ORCID,Yin Jun²^ORCID,Mak Pui-In²^ORCID,Gao Xiang³^ORCID,Luo Xun⁴^ORCID

Affiliation:

1. Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China (UESTC), Chengdu, China

2. Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, Macau, China

3. School of Micro-Nano Electronics, Zhejiang University, Hangzhou, China

4. Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China, Shenzhen, China

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/22/10666889/10449934.pdf?arnumber=10449934

Reference42 articles.

1. A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

2. A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

3. A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation

4. A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

5. Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication