A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

Author:

Chiu Wei-Hao,Huang Yu-Hsiang,Lin Tsung-Hsien

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 61 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display;Analog Integrated Circuits and Signal Processing;2023-11-10

2. A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier;International Journal of Electronics;2023-11-07

3. Fast locking Sampling PLL Using Phase Error Eliminator;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

4. A Locking Time Reduced PLL Reusing DCM Feedback Delay Tap in the FPGA Designs;2023 6th International Conference on Electronics Technology (ICET);2023-05-12

5. A Sub-Sampling Phase-Locked Loop With a Robust Agile-Locking Frequency-Locked Loop;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17

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