Fast locking Sampling PLL Using Phase Error Eliminator-Reference-Cited by-同舟云学术

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Fast locking Sampling PLL Using Phase Error Eliminator

Published:2023-10-24 Issue: Volume:783 Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
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Author:

Zhou Shengyuan¹,Xia Ziyao¹,Yang Chao¹,Liu Xiaoming¹,Wang Sheng¹,Jin Jing¹

Affiliation:

1. Shanghai Jiao Tong University(SJTU),Department of Micro/Nano Electronics,Shanghai,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10395954.pdf?arnumber=10395954

Reference12 articles.

1. An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO

2. A 23.6-38.3GHz Low-Noise PLL with Digital Ring Oscillator and Multi-Ratio Injection-Locked Dividers for Millimeter-Wave Sensing

3. A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

4. A low noise CMOS frequency synthesizer with dynamic bandwidth control

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