Author:
Bayer M.,Chomicz T.,James F.,McEntarfer P.,Mijuskovic D.,Porter J.
Cited by
2 articles.
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1. Fast locking Sampling PLL Using Phase Error Eliminator;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. Low-Jitter PLL Architectures;Clock Generators for SOC Processors