Low-Jitter PLL Architectures
Publisher
Springer-Verlag
Reference53 articles.
1. I. Novof, et. al., “Fully Integrated CMOS Phase-Locked Loop with 15 to 240MHz Locking Range and ±50 ps Jitter,” IEEE J. of Solid-State Circuits, vol. 30, no. 11, pp. 1259–1266, November 1995. 2. K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and Modeling of Mismatches in MOS Transistors for Precision Analog Design,” IEEE J. of Solid-State Circuits, vol. 21, pp. 1057–1066, Dec. 1986. 3. V. Manassewitsch, Frequency Synthesizers, Theory and Design, Boston: Wiley, 1987. 4. D. Boerstler, “A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340–612 MHz,” IEEE J. of Solid-State Circuits, vol. 34, no. 4, pp. 513–519, April 1999. 5. H. Ahn and D. Allstot, “A Low-Jitter 1.9-V CMOS PLL for UltraSPARC Microprocessor Applications,” IEEE J. of Solid-State Circuits, vol. 35, no. 3, pp. 450–454, March 2000.
|
|