Author:
Hee-Tae Ahn ,Allstot D.J.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
29 articles.
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1. A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01
2. Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-12
3. The McPAT Framework for Multicore and Manycore Architectures;ACM Transactions on Architecture and Code Optimization;2013-04
4. A fast-locking PLL with all-digital locked-aid circuit;International Journal of Electronics;2013-02
5. A single capacitor loop filter phase-locked loop with frequency voltage converter;Analog Integrated Circuits and Signal Processing;2012-10-18