A single capacitor loop filter phase-locked loop with frequency voltage converter
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-012-9978-5.pdf
Reference7 articles.
1. Gartner, F. M. (1980). Charge-pump phase-lock loop. IEEE Transactions on Communications, 28(11), 1849–1858.
2. Ahn, H. T., & Allstot, D. (2000). A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications. IEEE Journal of Solid-State Circuits, 35(3), 450–454.
3. Bashir, A., Li, J., Ivatury, K., Khan, N., Gala, N., Familia, N., et al. (2009). Fast lock scheme for phase-locked loop. In IEEE 2009 Custom Integrated Circuits Conference, San Jose (pp. 319–322).
4. Kim, J., Kim, J. K., Lee, B. J., Kim, N., Jeong, D. K., & Kim, W. (2008). A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits, 41(4), 899–908.
5. Lee, T. C., & Razavi, B. (2003). A stabilization technique for phase-locked frequency synthesizers. IEEE Journal of Solid-State Circuits, 38(6), 888–894.
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