Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
Author:
Affiliation:
1. Department of Information Engineering, University of Padova, Padua, Italy
2. Infineon Technologies Austria AG, Villach, Austria
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/10375801/10145092.pdf?arnumber=10145092
Reference44 articles.
1. A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS
2. A 28-GHz CMOS Direct Conversion Transceiver With Packaged $2 \times 4$ Antenna Array for 5G Cellular System
3. A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
4. A Transformer-Based Poly-Phase Network for Ultra-Broadband Quadrature Signal Generation
5. CMOS mixers and polyphase filters for large image rejection
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2. Investigation of Coupling Mechanisms for Efficient High Power and Low Phase Noise E-Band Quadrature VCOs in 130nm SiGe;IEEE Journal of Microwaves;2024-04
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4. Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
5. Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices;Annals of Emerging Technologies in Computing;2024-01-01
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