A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS-Reference-Cited by-同舟云学术

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A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS

Published:2018-12 Issue:12 Volume:53 Page:3576-3586
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Piri Farshad^ORCID,Bassi Matteo^ORCID,Lacaita Niccolo R.,Mazzanti Andrea^ORCID,Svelto Francesco

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8580626/08544058.pdf?arnumber=8544058

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Back-Gate Coupling Technique for Phase Error Correction in PLL-Based Quadrature VCOs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs;IEEE Journal of Solid-State Circuits;2024-01

4. A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness;IEEE Journal of Solid-State Circuits;2023-07

5. A 53–78 GHz Complementary Push–Push Frequency Doubler With Implicit Dual Resonance for Output Power Combining;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-03

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