A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator
Author:
Affiliation:
1. Technische Universität Berlin,Mixed Signal Circuit Design,Berlin,Germany,10587
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10557980.pdf?arnumber=10557980
Reference12 articles.
1. Sub-sampling PLL techniques
2. A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop
3. Low-Power and Low-Noise Millimeter-Wave SSPLL With Subsampling Lock Detector for Automatic Dividerless Frequency Acquisition
4. Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm
5. A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling
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