Sub-sampling PLL techniques
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7321938/7338356/07338420.pdf?arnumber=7338420
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS;Journal of Low Power Electronics and Applications;2023-12-17
2. A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier;IEEE Journal of Solid-State Circuits;2023-12
3. A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven Phase Demodulator;IEEE Journal of Solid-State Circuits;2023-09
4. A Spur Reduction Architecture for Integer-N Subsampling PLLs;2023 International Symposium on Signals, Circuits and Systems (ISSCS);2023-07-13
5. A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
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