A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling
Author:
Affiliation:
1. Technische Universität Berlin,Mixed Signal Circuit Design,Berlin,Germany,10587
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182081.pdf?arnumber=10182081
Reference12 articles.
1. Low-Power and Low-Noise Millimeter-Wave SSPLL With Subsampling Lock Detector for Automatic Dividerless Frequency Acquisition
2. A 93.4–104.8-GHz 57-mW Fractional-${N}$ Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology
3. A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference
4. A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture
5. A Charge Pump Current Mismatch Compensation Design for Sub-Sampling PLL
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1. A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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