Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA-Reference-Cited by-同舟云学术

Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA

Published:2022-12-14 Issue: Volume: Page:
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Container-title:2022 5th International Conference on Contemporary Computing and Informatics (IC3I)
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Author:

Kumar Keshav¹,Singh Vijay²,Mishra Gaurav³,Ravindra Babu. B⁴,Tripathi Nandita⁵,Kumar Pramod⁶

Affiliation:

1. University Institute of Computing Chandigarh University,Punjab,India

2. Graphic Era Deemed to be University,Department of Computer Science & Engineering,Dehradun,Uttarakhand,India

3. Amity University Uttar Pradesh,Amity School of Engineering & Tchnology,Graeter Noida,Uttar Pradesh,India

4. Adama Science and Technology University,CSE Department,Adama,Ethiopia

5. AIPS Amity University Greater Noida,the Institution,Uttar Pradesh,India

6. Lloyd Institute of Engineering and Technology,Department of ECE,Greater Noida,India

Publisher

IEEE

Link

Reference22 articles.

1. Resource-shared crypto-coprocessor of AES Enc/Dec with SHA-3;khalid;IEEE Transactions on Circuits and Systems I Regular Papers,2020

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1. SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06

2. AES Algorithm with Dynamic Shift Rows and Bit Permuted Mix Column;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14