SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA-Reference-Cited by-同舟云学术

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SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA

Published:2024-04-06 Issue: Volume:11 Page:1250-1254
ISSN:
Container-title:2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT)
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Author:

Kumar Keshav¹,NP Stenin²,Pandey Pushpanjali³,Pandey Bishwajeet²,Gohel Hardik⁴

Affiliation:

1. University Institute of Computing, Chandigarh University,Punjab,India

2. Astana IT University,Department of Intelligent System and Cyber Security,Kazaksthan

3. Cyber Security Cell, Gyancity Research Consultancy,Gurgoan,India

4. University of Houston,Texas,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10545643/10545610/10546070.pdf?arnumber=10546070

Reference20 articles.

1. Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

2. Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

3. Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA

4. FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology

5. Increasing cyber security by energy efficient implementation of DES algorithms on FPGA;Pandey;Journal of Green Engineering,2021

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