FPGA implementation of AES algorithm for high speed applications-Reference-Cited by-同舟云学术

FPGA implementation of AES algorithm for high speed applications

Published:2021-11-16 Issue: Volume: Page:
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Priya S. Sridevi Sathya,Karthigaikumar P.,Teja Narayana Ravi

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s10470-021-01959-z.pdf

Reference25 articles.

1. Karthigaikumar, P., & Baskaran, K. (2010). An ASIC implementation of low power and high throughput blowfish crypto algorithm. Microelectronics Journal, 41, 347–355.

2. National Institute of Standards and Technology (NIST). (2001). Advanced Encryption Standard (AES).

3. W.Stallings. (2005). Cryptography and Network Security 4th Eds, Prentice Hall. 58–309

4. Mali, Marko, Novak, Franc, & Biasizzo, Anton. (2005). Hardware implementation of AES algorithm. Journal of Electrical Engineering., 56, 265–269.

5. Zhang, Y., Wang, X. (2010). Pipelined Implementation of AES Encryption based on FPGA". In: Proceedings of IEEE international Conference on Information Theory and Information Security (ICITIS). 170–173.

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