Energy-efficient implementation of AES algorithm on 16nm FPGA

Author:

Pandey Bishwajeet,Bisht Vaishnavi,Akbar Hussain Dil Muhammad,Jamil Mohsin,Hasan Mohammad Kamrul

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. HSTL IO Standards Based Low Power Implementation of Elliptic Curve Cryptography (ECC) on FPGA;2024 IEEE 4th International Conference on Smart Information Systems and Technologies (SIST);2024-05-15

2. Deep Learning Method for Power Side-Channel Analysis on Chip Leakages;Elektronika ir Elektrotechnika;2023-12-13

3. Optimization Technique for Deep Learning Methodology on Power Side Channel Attacks;2023 33rd International Telecommunication Networks and Applications Conference;2023-11-29

4. Multi-Layer Perceptrons and Convolutional Neural Networks Based Side-Channel Attacks on AES Encryption;2023 International Conference on Engineering Technology and Technopreneurship (ICE2T);2023-08-15

5. Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA;2022 5th International Conference on Contemporary Computing and Informatics (IC3I);2022-12-14

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