Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells-Reference-Cited by-同舟云学术

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Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

Published:2006-12 Issue:12 Volume:53 Page:3012-3019
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kim Bomsoo,Kwon Wook-Hyun,Baek Chang-Ki,Son Younghwan,Park Chan-Kwang,Kim Kinam,Kim Dae M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/4016323/04016346.pdf?arnumber=4016346

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A new erase method for scaled NAND flash memory device;Microelectronics Reliability;2017-05

2. Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure;Japanese Journal of Applied Physics;2014-06-01

3. Multi-bit NAND Flash memories for ultra high density storage devices;Advances in Non-volatile Memory and Storage Technology;2014

4. Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH;IEEE Journal of Solid-State Circuits;2013-04

5. Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects;Solid-State Electronics;2011-09

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