A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx2/147/3344/05727447.pdf?arnumber=5727447
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Poly-Si Finlike Thin-Film Transistors With Various Wide Drain Designs for Radio Frequency and 3-D Integrated Circuits;IEEE Transactions on Electron Devices;2020-06
2. Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory;Japanese Journal of Applied Physics;2015-03-13
3. Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass;IEICE Transactions on Electronics;2014
4. Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate;IEICE Transactions on Electronics;2013
5. Self-Aligned Metal Double-Gate Low-Temperature Polycrystalline Silicon Thin-Film Transistors on Glass Substrate Using Back-Surface Exposure;Japanese Journal of Applied Physics;2011-02-21
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